This disclosure relates to a semiconductor device arrangement with at least one power transistor and at least one gate resistor, the power transistor having an extremely high switching speed owing to very low device capacitances. In the turn-off process, the so-called decommutation process, however, current and voltage overlap in the power transistor. To minimize any turn-off losses resulting from this, it is possible to turn off the channel current very fast by small external gate series resistors.
Turn-off losses can also be reduced by using the output capacitance Ca as a turn-off unloading capacitor. In this process, the load current commutates completely into the output capacitance Ca. As a result, the semiconductor device suffers virtually no heat losses in the turn-off process, but only a capacitive displacement current into the output capacitance Ca with an energy content ECa of
                              E          ⁢                                          ⁢          Ca                =                              ∫            0                          u              DS                                ⁢                      Ca            ·            U            ·                          ⅆ              U                                                          (                  equation          ⁢                                          ⁢          1                )            
wherein uDS represents the rising drain-source voltage in the turn-off process. From this can be derived the capacitive energy content of the semiconductor device in the off state at a voltage UDS. This energy content can be minimized by reducing the value of the output capacitance Ca while reducing the size of the component.
In a switching process modified as described above by using the output capacitance Ca, the voltage increase during the turn-off process is however no longer controlled by the gate, but only by the load current IL to be disconnected. The voltage increase du/dt is determined by the load current IL in a linear manner and is inversely proportional to the output capacitance Ca withdu/dt=IL/Ca  (equation 2),
Wherein IL represents the load current and Ca represents the output capacitance of the power transistor.
By reducing the dimensions of the device, the output capacitance Ca is reduced to a very low value, so that at high current peaks the voltage increase du/dt reaches values which may significantly exceed the permissible breakdown voltage. Owing to the intrinsic structure of the semiconductor devices, the output capacitance Ca is voltage-dependent, so that, based on the above equation 2, the value of Ca changes as du/dt increases during the turn-off process. This change causes both a change of the capacitive displacement current for the output capacitance Ca and a change of the capacitive displacement current at the gate electrode.
In a non-linear condition, i.e. if there are parasitic inductances in the drive circuit, the change of the gate current induces a reverse voltage and may result in oscillations, in particular if the exciting voltage, is amplified by the power transistor. This results in an upper limit frequency via the charge of the input capacitance of the power transistor and the through-conductivity of the power transistor. In high-voltage devices, this may be significantly lower than the inherent resonance of the serial oscillator circuit made up of the drain-gate capacitance and the gate inductance. Oscillations during the turn-off process of such power transistors are undesirable, as they affect the EMC (electromagnetic compatibility) of the power transistor.
The fast and, with the aid of the output capacitance, nearly loss-free switching of power transistors is further limited by a very high current chopping in the power circuit. If the power transistor is turned off in a completely unloaded state, the load current completely commutates into the output capacitance Ca. In this process, the gate voltage may fall below the Miller plateau at full load current and even be reduced to zero. The Miller plateau is the potential at the insulated gate which still ensures that the channel of a field effect power transistor remains open.
If the power transistor as a switch reaches the externally preset link voltage, the switch can supply the load current. The di/dt resulting from this will cause a voltage reduction at the power transistor via the existing source inductances and, if the gate potential remains constant, contribute to an effective biasing of the channel. It has however been found that, owing to the capacitive coupling between gate and source, the gate potential follows a steep voltage reduction to source, resulting on the one hand in an incomplete biasing of the channel and on the other hand in an excessively high voltage amplitude at the gate.
In combination with the gate inductances, the rapid voltage change at the gate due to the capacitive coupling between gate and source also excites undesirable oscillations. Both effects are due to the inductances existing in a power transistor between the control electrode and a switching electrode. Such inductances are built up by the conductor routing to the gate connections of the power transistor within the semiconductor device and in part by the connecting elements forming induction loops between external contacts of the semiconductor device arrangement and the internal contact surfaces on the semiconductor chip of the power transistor.
For these and other reasons, there is a need for the present invention.